Project information

Month-long project to develop a RISC-V CPU compliant with the RV32I instruction set. Built in SystemVerilog in a team of 4, with integrated functionality for caching and pipelining to optimize performance. A complimentary robust set of tests were also produced and the entire process of development was thoroughly documented.

I primarily worked on designing and coding our CPU, while also acting as a project manager and structuring the documentation.